Job responsibilities
Job Responsibilities：
1. Responsible for design works in developing large chips, including but not limited to: clock/reset structure, synthesis and timing signoff related work;
2. Responsible for writing design documents, or writing RTL according to existing design documents;
3. Responsible for digital circuit design, RTL coding, verification, synthesis and timing signoff work;
4. The following relevant experience is preferred: peripheral IO related design work such as SDIO, SPI, UART, etc.
Requirements
Qualifications
1. Master's degree or above in microelectronics, computer, electronic engineering and other related majors, with more than 3 years of relevant work experience;
2. Understand the front-end and back-end processes of chip development;
3. Rich experience with Verilog, familiar with more than one script language(shell, TCL, Perl, python are acceptable), and experience in common EDA usage;
4. Strong team coordination ability, good at communication and problem solving.
