Job responsibilities
The role of a Senior Design Verification Engineer includes but is not limited to:
1. Develop test plans, tests & coverage plans as well as define verification methodology & testbenches
2. Develop verification environment to verify system will meet design requirements.
3. Write test cases and execute test plans for complex designs.
4. Close functional/code coverage for assigned functional blocks.
5. Lead small teams of verification engineers and mentor engineers.
6. Collaborate with teams across sites and geographies.
"
Requirements
Minimum Qualifications:
1. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or in a related field of study.
2. 5+ years of experience in Design Verification.
3. Knowledge of UVM and SystemVerilog based verification methodologies.
4. Knowledge of computer architecture and digital design fundamentals.
5. Knowledge of Verilog or SystemVerilog, digital simulation and debug.
6. Experience with Python, Perl, or similar scripting language.
7. Ability to work independently to deliver the project goals.
8. Excellent interpersonal skills and able to take on diverse challenges.
Preferred Qualifications:
1. Graduate/post-graduate degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field of study.
2. Experience in SoC design verification.
3. Experience with scripting languages.
4. Low power experience (e.g., UPF).
5. Experience with Ethernet, PCIe and/or DDR protocols.
6. Experience with NOC and/or CPU.
7. Experience with C/C++, assembly is a plus.
8. Experience of team management/mentoring."
